1. Field of the invention
The present invention relates to a digital driver for display devices. The invention further relates to a display device including the digital driver according to the invention. Further, as the display medium of the display device including the digital driver according to the invention, liquid crystal, organic EL or the like can be used.
2. Description of the Related Art
Recently, the technique of fabricating a semiconductor device such as, e.g., thin-film transistors (TFT), constituted in such a manner that a semiconductor thin-film is formed on a cheap glass substrate has been rapidly developed. It is because the demand for active matrix semiconductor display devices (particularly, active matrix liquid crystal display devices) is growing.
An active matrix liquid crystal display device is constituted in such a manner that a TFT is disposed in each of several tens to several millions of picture element regions matrixwise disposed, and the electric charges entering and leaving each picture element electrode are controlled by the switching function of the TFT.
Among such active matrix liquid crystal display devices, a digital drive type active matrix liquid crystal display device which can be driven at high speed is attracting attention as display devices are becoming more and more fine and precise and their picture quality is more and more improved. The digital drive type active matrix liquid crystal display device includes a digital driver for processing digital data.
FIG. 15 shows a known digital drive type active matrix liquid crystal display device. This known digital drive type active matrix liquid crystal display device comprises a shift register 2001, data lines (a to d) 2002 to which digital data are inputted, latch circuits 1 (LAT1) 2003, latch circuits 2 (LAT2) 2004, a latch pulse line 2005, D/A converter circuits 2006, a gradation voltage lines 2007 for feeding a voltage to the D/A converter circuits 2006, source signal lines 2008, a shift register 2009 at the gate signal line side, gate signal lines (scanning lines) 2010, and picture element TFTs 2011. Here, a 4-bit digital drive type active matrix liquid crystal display device is shown by way of example. The latch circuits 1 and the latch circuits 2 (LAT1 and LAT2) are each shown in the state in which four latch circuits corresponding to the respective bits of the digital data are put together for convenience""sake.
In, e.g., Matsueda et al.: xe2x80x9cLow Temperature Poly-Si TFT-LCD with integrated 6-bit Digital Data Driversxe2x80x9d (SID 96 DIGEST pp. 21 to 24), known digital drive type active matrix liquid crystal display devices are described.
In case of the known digital drive type active matrix liquid crystal display device shown in FIG. 15, the digital signals (digital video data) fed to the data lines (a to d) 2002 are written into the group of latch circuits (LAT1) one after another in accordance with the timing signals from the shift register.
The time spent until the writing of the digital signal into the LAT1 group is completely terminated is called one line period. In other words, the time interval from the point of time when the writing of the digital signals into the leftmost LAT1 is started to the point of time when the writing of the digital signals into the rightmost LAT1 is completed is one line period.
After the writing of the digital signals into the LAT1 group, the digital signals thus written into the LAT1 group are simultaneously sent out and written into the LAT2 group, when a latch pulse flows to the latch pulse line, in tune with the operating timing of the shift register.
Into the LAT1 group which has completely sent out the digital signals to the LAT2 group, the writing of digital signals is successively carried out again in accordance with the signals from the shift register.
During this second one-line period, a voltage corresponding to the digital signals sent out to the LAT2 group in step with the start of the second one-line period is fed to a source signal line. The driver referred to here by way of example executes the conversion of the digital signals to a gradation voltage by selecting one of 16 gradation voltages by the D/A converter circuits.
The thus selected gradation voltage is fed to the corresponding source signal line during one line. By the scanning signal from the shift register at the gate signal line side, the corresponding TFT is switched, whereby the liquid crystal molecules are driven.
By repeating the above-mentioned operation by a number of times corresponding to the number of the scanning lines, one frame is formed. In general, in an active matrix liquid crystal display device, pictures of 60 frames are re-written for one second.
As shown in FIG. 15, in the known digital driver, the data lines (a to d) 2002 to which digital data fed must feed the digital data to all the latch circuits 1 (2003), and thus, the laid-around length of the wirings of the data lines in the digital driver is very large. As a result, the load (the parasitic capacitance and resistance) of the data lines 2002 becomes large, so that the delay of the digital data, so-called the extended transition time of the digital data is increased.
By the use of the known digital driver, the display of pictures cannot be executed on the basis of accurate digital data, due to the above-mentioned delay of the digital data and the extended transition time of the digital data in some cases, and thus, good display could not be made in some cases.
Thus, the present invention has been achieved in view of the above-mentioned problem; the invention thus provides a digital driver for display devices which can prevent the delay of the digital data and the extended transition time of the digital data to make good display and also provides a display device including the just-mentioned digital driver.
In the digital driver according to the invention, digital data are successively inputted to a shift register, whereby the digital data are shifted in the shift register, and the output thereof is sent out to latch circuits.
In the digital driver according to the invention, digital data are inputted directly to the shift register, so that the distance over which the data lines are laid around can be shortened; and thus, the increase in load due to the laying-around of the data lines which has so far been a problem can be prevented, and the delay of the digital data and the extended transition time of the digital data can be prevented.
The constitution of the invention will be described below.
According to a first aspect of the invention, a digital driver comprises
a shift register circuit including a plurality of register circuits, and
a latch circuit array including a plurality of latch circuits,
wherein digital data are inputted to the shift register circuit,
the digital data successively shift through the plurality of register circuits, and
to the plurality of latch circuits, the outputs of the digital data from the corresponding ones of the register circuits are inputted.
According to a second aspect of the invention, a digital driver comprises
a shift register circuit which has a register circuit at the first stage, a register circuit at the second stage, . . . , a register circuit at the (nxe2x88x921)th stage and a register circuit at the nth stage (wherein n stands for a natural number), and
a latch circuit array including a first latch circuit, a second latch circuit, . . . , an (nxe2x88x921)th latch circuit and an nth latch circuit, wherein first digital data, second digital data, . . . , an (nxe2x88x921)th digital data and an nth digital data are successively inputted to the register circuit at the first stage,
the output of the register circuit at the first stage, the output of the register circuit at the second stage, . . . , the output of the register circuit at the (nxe2x88x921)th stage and the output of the register circuit at the nth stage are respectively sent out to the first latch circuit, the second latch circuit, . . . , the (nxe2x88x921)th latch circuit and the nth latch circuit,
the instant the first digital data is inputted to the register circuit at the nth stage, the oscillation of a clock signal inputted to the shift register circuit stops, and the nth digital data, the (nxe2x88x921)th digital data, . . . , the second digital data and the first digital data which are respectively held in the register circuit at the first stage, the register circuit at the second stage, . . . , the register circuit at the (nxe2x88x921)th stage and the register circuit at the nth stage are respectively read into the first latch circuit, the second latch circuit, . . . , the (nxe2x88x921)th latch circuit and the nth latch circuit.
According to a third aspect of the invention, a display device comprises
TFTs disposed in a matrix shape,
a source driver, and
a gate driver,
wherein the source driver comprises a shift register circuit which includes a plurality of register circuits and a latch circuit array which includes a plurality of latch circuits,
to the shift register circuit, digital data are inputted,
the digital data successively shift through the plurality of register circuits, and,
to the plurality of latch circuits, the digital data outputs from the corresponding ones of the register circuits are inputted.
According to a fourth aspect of the invention, a display device comprises
TFTs disposed in a matrix shape,
a source driver, and
a gate driver,
wherein the source driver comprises a shift register circuit which includes a register circuit at the first stage, a register circuit at the second stage, . . . , a register circuit at the (nxe2x88x921)th stage and a register circuit at the nth stage (wherein n stands for a natural number) and a latch circuit array which includes a first latch circuit, a second latch circuit, . . . , an (nxe2x88x921)th latch circuit and an nth latch circuit,
first digital data, second digital data, . . . , (nxe2x88x921)th digital data and nth digital data are successively inputted to the register circuit at the first stage, the output of the register circuit at the first stage, the output of the register circuit at the second stage, . . . , the output of the register circuit at the (nxe2x88x921)th stage and the output of the register circuit at the nth stage are respectively sent out to the first latch circuit, the second latch circuit, . . . , the (nxe2x88x921)th latch circuit and the nth latch circuit, and
the instant the first digital data is inputted to the register circuit at the nth stage, the oscillation of a clock signal inputted to the shift register circuit stops, so that the nth digital data, the (nxe2x88x921)th digital data, . . . , the second digital data and the first digital data which are respectively held in the register circuit at the first stage, the register circuit at the second stage, . . . , the register circuit at the (nxe2x88x921)th stage and the register circuit at the nth stage are respectively taken into the first latch circuit, the second latch circuit, . . . , the (nxe2x88x921)th latch circuit and the nth latch circuit.
Here, description will be made on the mode for carrying out the invention.
FIG. 1 will be referred to. FIG. 1 is a circuit block diagram showing the shift register circuit and the latch circuit array of the m-bit digital driver according to an embodiment of the invention. The shift register circuit and the latch circuit array shown in FIG. 1 process the first bit of m-bit digital data. Thus, the m-bit digital driver according to this embodiment comprises m such circuits as shown in FIG. 1.
The reference numeral 100 denotes a shift register circuit. The shift register circuit 100 includes n register circuits 101 (DFF1 to DFFn) (wherein n stands for a natural number) at a first stage to the nth stage. To the n register circuits (DFF1 to DFFn) in the shift register circuit, a clock signal line 102, a clock-back signal line 103 and a digital data line 104 are connected, so that, by the respective signal lines, a clock signal (CLK), a clock-back signal (CLKB) which is the inversion signal of the clock signal, and digital data (DIGITAL DATA) are inputted. Further, the digital data (DIGITAL DATA) fed to the shift register circuit 100 are inputted to the register circuit (DFF1) at the first stage.
Numeral 110 denotes a latch circuit array. The latch circuit array 110 includes first to nth latch circuits 111 (LATCH1 to LATCHn). To the latch circuits 111 (LATCH1 to LATCHn) of the latch circuit array 110, a latch signal line 112 and a latch-back signal line 113 are connected, and thus, by the respective signal lines, a latch signal (LAT) and a latch-back signal (LATB) which is the inversion signal of the latch signal are inputted.
Here, the operation of the digital driver according to the invention will be described, referring to FIG. 2. FIG. 2 shows a timing chart pertaining to the shift register circuit and the latch circuit array of the source driver according to this embodiment.
To the register circuit DFF1 at the first stage of the source driver, there are inputted a lock signal (CLK), a clock-back signal (CLKB), and the digital data fed to the source driver. To the register circuit DFF1, the first digital data (1_1), the second digital data (2_1), the third digital data (3_1), . . . , the (nxe2x88x921)th digital data (nxe2x88x921_1) and the nth digital data (n_1) are successively inputted (DFF1 input shown in FIG. 2).
The DFF1 shifts and outputs the inputted data successively (DFF1 output and S1 shown in FIG. 2) on the basis of the clock signal (CLK) and the clock-back signal (CLKB), thus successively sending the digital data out to the register circuit DFF2 at the following stage. The reference symbol t1 stands for the pulse width of one-bit digital data.
To the register circuit DFF2 at the second stage, the digital data outputted from the DFF1 are inputted; and the register circuit DFF2 successively shifts and outputs the inputted digital data (DFF2 outputs and S2 shown in FIG. 2) on the basis of the clock signal (CLK) and the clock-back signal (CLKB), thus successively sending out the digital data to the register circuit DFF3 at the following stage.
As stated above, the digital data inputted to the register circuit DFF1 at the first stage are shifted through the register circuits one after another on the basis of the clock signal (CLK) and the clock-back signal (CLKB), finally becoming the output of the register circuit DFFn at the final stage (the nth stage) (the DFFn output and Sn shown in FIG. 2).
The period during which the digital data (1_1) inputted to the register circuit DFF1 at the first stage become the output of the register circuit DFFn at the final stage is called line period (TL). During this line period (TL), the clock signal (CLK) and the clock-back signal (CLKB) are continuously fed to all the register circuits (DFF1 to DFFn). Further, during the line period (TL), the latch signal (LAT) and the latch-back signal (LATB) are controlled so that new digital data may not be inputted to the latch circuits.
Further, between a line period (TL) and the next line period (TL), a horizontal retrace line period (THB) exists. During this horizontal retrace line period (THB), the oscillation of the clock signal (CLK) and the clock-back signal (CLKB) is stopped (See FIG. 2). By this measure, during the horizontal retrace line period (THB), the register circuits (DFF1 to DFFn) hold the outputs (S1 to Sn) of the digital data and thus output the digital data to corresponding ones of the first to nth latch circuits (LATCH1 to LATCHn) without fail.
As shown in FIG. 2, during this latch period (TLA), the output (nxe2x88x921) of the register circuit DFF1 at the first stage is inputted to the first latch circuit LATCH1, the output (nxe2x88x921_1) of the register circuits DFF1 at the second stage is inputted to the second latch circuit LATCH2, and the output (1_1) of the register circuit DFF1 at the nth stage is inputted to the nth latch circuit LATCHn. Further, the sum of the line period (THB) and the horizontal retrace line period (THB) is called horizontal period (TH).
During the horizontal retrace line period (THB), the latch signal (LAT) and the latch-back signal (LATB) are inputted within the latch period (TLA), and the respective latch circuits (LATCH1 to LATCHn) take in the digital data held in the register circuits.
In this way, the digital data (n_1 to 1_1) are taken into the all the first to nth latch circuits (LATCH1 to LATCHn), respectively. Thus, it can be understood that the digital data (n_1 to 1_1) are taken into the nth to first latch circuits (LATCHn to LATCH1) in the order of the digital data being inputted.
After the termination of the horizontal retrace line period (THB), a line period (TL) starts again, and the oscillation of the clock signal (CLK) and the clock-back signal (CLKB) is resumed. Then the digital data inputted to the resister circuits DFF1 at the first stage shift through the register circuits one after another on the basis of the clock signal (CLK) and the clock-back signal (CLKB).
By repeating the above-mentioned operation, the digital data inputted to the shift register circuit 100 can be outputted in parallel to the latch circuit array 110. In this specification, a driving method as according to the present invention will be called the data shift system in view of the fact that the digital data shift through the registers.
The digital data outputted to the latch circuit array 110 are converted into analog data by D/A converters and the like and outputted to the display portion of the display device.
In case of the data shift system according to the present invention, the data are inputted directly to the shift register circuit, and the data themselves shift one after another, so that, while the clock signal (CLK) and the clock-back signal (CLKB) are fed to the shift register circuit, the output digital data of the respective register circuits (DFF1 to DFFn) are rewritten successively. In order to obtain the digital data to be originally maintained as the outputs of the respective register circuits, it is necessary to ensure that the output digital data of the respective register circuits are not rewritten successively. In other words, in order to ensure that, when the digital data are established as the outputs of the respective register circuits, the oscillation of the clock signal (CLK) and the clock-back signal (CLKB) must be stopped so that the digital data can be held. Further, it is immediately after the termination of the line period that the output digital data of the respective register circuits are established, and, when the next line period starts, new digital data are inputted to the register circuits (DFF1) at the first stage. Thus, it follows that the period during which the oscillation of the clock signal (CLK) and the clock-back signal (CLKB) is to be stopped is the horizontal retrace line period (THB) between a line period (TL) and the next line period (TL).
In the digital driver according to the invention, the digital data are inputted directly to the shift registers, so that the laying-around distance of the data lines can be shortened; and thus, the increase in load due to the laying-around of the data lines which has so far been a problem to be overcome can be prevented, and thus, the delay of the digital data and the extended transition time of the digital data can be prevented.